Invention Grant
- Patent Title: Method for manufacturing wafer level chip scale package structure
- Patent Title (中): 制造晶圆级芯片级封装结构的方法
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Application No.: US10711536Application Date: 2004-09-24
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Publication No.: US07170167B2Publication Date: 2007-01-30
- Inventor: Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
- Applicant: Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
- Applicant Address: TW Hsinchu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.
Public/Granted literature
- US20060065976A1 METHOD FOR MANUFACTURING WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE Public/Granted day:2006-03-30
Information query
IPC分类: