Invention Grant
US07174357B2 Circuitry for carrying out division and/or square root operations requiring a plurality of iterations 有权
用于执行需要多次迭代的划分和/或平方根操作的电路

Circuitry for carrying out division and/or square root operations requiring a plurality of iterations
Abstract:
Circuitry for carrying out an arithmetic operation requiring a plurality of iterations, such as division or square root operations, utilizes N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry includes at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.
Public/Granted literature
Information query
Patent Agency Ranking
0/0