发明授权
- 专利标题: Multi processor enqueue packet circuit
- 专利标题(中): 多处理器入队包电路
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申请号: US10171957申请日: 2002-06-14
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公开(公告)号: US07174394B1公开(公告)日: 2007-02-06
- 发明人: Trevor Garner , Kenneth H. Potter , Robert Leroy King , William R. Lee
- 申请人: Trevor Garner , Kenneth H. Potter , Robert Leroy King , William R. Lee
- 申请人地址: US CA San Jose
- 专利权人: Cisco Technology, Inc.
- 当前专利权人: Cisco Technology, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Cesari and McKenna LLP
- 主分类号: G06F3/00
- IPC分类号: G06F3/00
摘要:
The present invention provides a system and method for a plurality of independent processors to simultaneously assemble requests in a context memory coupled to a coprocessor. A write manager coupled to the context memory organizes segments received from multiple processors to form requests for the coprocessor. Each received segment indicates a location in the context memory, such as an indexed memory block, where the segment should be stored. Illustratively, the write manager parses the received segments to their appropriate blocks of the context memory, and detects when the last segment for a request has been received. The last segment may be identified according to a predetermined address bit, e.g. an upper order bit, that is set. When the write manager receives the last segment for a request, the write manager (1) finishes assembling the request in a block of the context memory, (2) enqueues an index associated with the memory block in an index FIFO, and (3) sets a valid bit associated with memory block. By setting the valid bit, the write manager prevents newly received segments from overwriting the assembled request that has not yet been forwarded to the coprocessor. When an index reaches the head of the index FIFO, a request is dequeued from the indexed block of the context memory and forwarded to the coprocessor.
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