An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The arbiter may arbitrate for two or more slave devices, or may arbitrate multiple master device requests directed to the same slave device. The arbiter frequency may be variable, and may be predicted based on, e.g., prior bus activity. If only one bus transaction request is pending, the arbiter frequency may equal the bus frequency. The results of an earlier arbitration decision may be utilized to more intelligently make subsequent arbitration decisions in the same bus frequency clock cycle.