发明授权
- 专利标题： Method and device for adjusting lane ordering of peripheral component interconnect express
- 专利标题（中）： 调整外围组件互连通道排序的方法和装置
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申请号： US10921116申请日： 2004-08-19
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公开(公告)号： US07174412B2公开(公告)日： 2007-02-06
- 发明人: Chih-Jung Lin
- 申请人： Chih-Jung Lin
- 申请人地址： TW Taipei
- 专利权人： Genesys Logic, Inc.
- 当前专利权人： Genesys Logic, Inc.
- 当前专利权人地址： TW Taipei
- 代理机构： Rosenberg, Klein & Lee
- 主分类号： G06F13/00
- IPC分类号： G06F13/00
摘要：
A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral device. The peripheral device replies the second packet associated with the second PCI Express lane ordering. Whether the PCI Express lane ordering is correct is determined in response to said second packet. The first PCI Express lane ordering is adjusted while the first PCI Express lane ordering does not match the second PCI Express lane ordering. Preferably, the adjusted PCI Express lane order matches the normal order or the reverse order. Then, reset and reinitialize the peripheral device. The resetting step can be accomplished by sending reset packets, or changing the common mode voltage level in order to reset the bridge chipset of the PC.