Invention Grant
US07176483B2 Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
有权
在电连接处去除半导体的费米能级的方法以及包含这种结的装置的方法
- Patent Title: Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
- Patent Title (中): 在电连接处去除半导体的费米能级的方法以及包含这种结的装置的方法
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Application No.: US10753504Application Date: 2004-01-07
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Publication No.: US07176483B2Publication Date: 2007-02-13
- Inventor: Daniel E. Grupp , Daniel J. Connelly
- Applicant: Daniel E. Grupp , Daniel J. Connelly
- Applicant Address: US CA Pacific Palisades
- Assignee: Acorn Technologies, Inc.
- Current Assignee: Acorn Technologies, Inc.
- Current Assignee Address: US CA Pacific Palisades
- Agency: Sonnenschein Nath & Rosenthal LLP
- Main IPC: H01L39/00
- IPC: H01L39/00

Abstract:
An electrical junction that includes a semiconductor (e.g., C, Ge, or an Si-based semiconductor), a conductor, and an interface layer disposed therebetween. The interface layer is sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm2, and in some cases a minimum specific contact resistance.
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