Invention Grant
- Patent Title: Method and circuit for error correction, error correction encoding, data reproduction, or data recording
- Patent Title (中): 用于纠错,纠错编码,数据再现或数据记录的方法和电路
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Application No.: US10714931Application Date: 2003-11-18
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Publication No.: US07178088B2Publication Date: 2007-02-13
- Inventor: Yuichi Hashimoto , Yuji Takagi , Makoto Usui , Naohiro Kimura , Yoshikazu Yamamoto
- Applicant: Yuichi Hashimoto , Yuji Takagi , Makoto Usui , Naohiro Kimura , Yoshikazu Yamamoto
- Applicant Address: JP Osaka
- Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee: Matsushita Electric Industrial Co., Ltd.
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: JP2002-333391 20021118; JP2003-169065 20030613
- Main IPC: G11B20/18
- IPC: G11B20/18

Abstract:
Data is read from a recording medium and the reproduced data is deinterleaved and stored to a first memory while input/output to/from the first memory is arbitrated. It is determined whether a predetermined number of data units is stored to the first memory. Based on the result data, it is determined whether transfer of the data stored in first memory to a second memory is permitted. If data transfer is permitted, the reproduced data is transferred from the first memory to the second memory, during which time input/output to/from the second memory is arbitrated. The reproduced data stored to the second memory is then error corrected, and user data contained in the error corrected reproduction data is externally output from the second memory.
Public/Granted literature
- US20040225946A1 Method and circuit for error correction, error correction encoding, data reproduction, or data recording Public/Granted day:2004-11-11
Information query
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