发明授权
- 专利标题: Method and circuit for error correction, error correction encoding, data reproduction, or data recording
- 专利标题(中): 用于纠错,纠错编码,数据再现或数据记录的方法和电路
-
申请号: US10714931申请日: 2003-11-18
-
公开(公告)号: US07178088B2公开(公告)日: 2007-02-13
- 发明人: Yuichi Hashimoto , Yuji Takagi , Makoto Usui , Naohiro Kimura , Yoshikazu Yamamoto
- 申请人: Yuichi Hashimoto , Yuji Takagi , Makoto Usui , Naohiro Kimura , Yoshikazu Yamamoto
- 申请人地址: JP Osaka
- 专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人: Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址: JP Osaka
- 代理机构: Wenderoth, Lind & Ponack, L.L.P.
- 优先权: JP2002-333391 20021118; JP2003-169065 20030613
- 主分类号: G11B20/18
- IPC分类号: G11B20/18
摘要:
Data is read from a recording medium and the reproduced data is deinterleaved and stored to a first memory while input/output to/from the first memory is arbitrated. It is determined whether a predetermined number of data units is stored to the first memory. Based on the result data, it is determined whether transfer of the data stored in first memory to a second memory is permitted. If data transfer is permitted, the reproduced data is transferred from the first memory to the second memory, during which time input/output to/from the second memory is arbitrated. The reproduced data stored to the second memory is then error corrected, and user data contained in the error corrected reproduction data is externally output from the second memory.
公开/授权文献
信息查询
IPC分类: