Invention Grant
- Patent Title: Low profile stacking system and method
- Patent Title (中): 薄型堆叠系统和方法
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Application No.: US11011469Application Date: 2004-12-14
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Publication No.: US07180167B2Publication Date: 2007-02-20
- Inventor: Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
- Applicant: Julian Partridge , James W. Cady , James Wilder , David L. Roper , James Douglas Wehrly, Jr.
- Applicant Address: US TX Austin
- Assignee: Staktek Group L. P.
- Current Assignee: Staktek Group L. P.
- Current Assignee Address: US TX Austin
- Agency: Fish & Richardson P.C.
- Agent J. Scott Denko
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or to the integrated circuit device to be mounted. The integrated circuit device is positioned to contact the contacts of the substrate. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
Public/Granted literature
- US20050146031A1 Low profile stacking system and method Public/Granted day:2005-07-07
Information query
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