发明授权
US07180779B2 Memory architecture with enhanced over-erase tolerant control gate scheme
有权
具有增强的过擦除宽容控制门控方案的存储架构
- 专利标题: Memory architecture with enhanced over-erase tolerant control gate scheme
- 专利标题(中): 具有增强的过擦除宽容控制门控方案的存储架构
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申请号: US11178965申请日: 2005-07-11
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公开(公告)号: US07180779B2公开(公告)日: 2007-02-20
- 发明人: Nicola Telecco , Victor Nguyen
- 申请人: Nicola Telecco , Victor Nguyen
- 申请人地址: US CA San Jose
- 专利权人: Atmel Corporation
- 当前专利权人: Atmel Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Schneck & Schneck
- 代理商 Thomas Schneck
- 主分类号: G11C11/34
- IPC分类号: G11C11/34
摘要:
The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.
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