发明授权
- 专利标题: Clock synchronization backup mechanism for circuit emulation service
- 专利标题(中): 电路仿真服务的时钟同步备份机制
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申请号: US10888421申请日: 2004-07-09
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公开(公告)号: US07191355B1公开(公告)日: 2007-03-13
- 发明人: Michel Ouellette , Jeganathan Markandu , James Aweya , Delfin Montuno
- 申请人: Michel Ouellette , Jeganathan Markandu , James Aweya , Delfin Montuno
- 申请人地址: CA
- 专利权人: Nortel Networks Limited
- 当前专利权人: Nortel Networks Limited
- 当前专利权人地址: CA
- 代理机构: McGuinness & Manaras LLP
- 主分类号: G06F1/12
- IPC分类号: G06F1/12 ; H04L12/28
摘要:
A clock synchronization backup mechanism is disclosed for maintaining clock synchronization during periods of degraded synchronization. The clock synchronization backup mechanism includes a jitter buffer having a fill value at a given sample time which is compared with a threshold. When the jitter buffer fill value exceeds the threshold, a non-normal condition is registered and the local clock frequency is set to a combination of a long-term frequency setting plus a threshold sensitive frequency adjustment. The clock synchronization backup mechanism is particularly useful for overcoming residual errors accumulated due to temperature change, oscillator degradation, and a variety of other system perturbations problematical for clock synchronization mechanisms known in the art.
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