发明授权
US07199011B2 Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon
有权
通过并入碳来减少晶体管栅极到源极/漏极重叠电容的方法
- 专利标题: Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon
- 专利标题(中): 通过并入碳来减少晶体管栅极到源极/漏极重叠电容的方法
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申请号: US10620492申请日: 2003-07-16
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公开(公告)号: US07199011B2公开(公告)日: 2007-04-03
- 发明人: Majid Movahed Mansoori , Alwin Tsao , Antonio Luis Pacheco Rotondaro , Brian Ashley Smith
- 申请人: Majid Movahed Mansoori , Alwin Tsao , Antonio Luis Pacheco Rotondaro , Brian Ashley Smith
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Jacqueline J. Garner; W. James Brady, III; Frederick J. Telecky, Jr.
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.
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