A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.