发明授权
US07218152B2 System and method for reducing power consumption associated with the capacitance of inactive portions of a multiplexer
有权
用于降低与多路复用器的非活动部分的电容相关联的功耗的系统和方法
- 专利标题: System and method for reducing power consumption associated with the capacitance of inactive portions of a multiplexer
- 专利标题(中): 用于降低与多路复用器的非活动部分的电容相关联的功耗的系统和方法
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申请号: US11033612申请日: 2005-01-12
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公开(公告)号: US07218152B2公开(公告)日: 2007-05-15
- 发明人: Hiroaki Murakami , Osamu Takahashi , Shoji Onishi
- 申请人: Hiroaki Murakami , Osamu Takahashi , Shoji Onishi
- 申请人地址: JP Tokyo US NY Armonk
- 专利权人: Kabushiki Kaisha Toshiba,International Business Machines Corporation
- 当前专利权人: Kabushiki Kaisha Toshiba,International Business Machines Corporation
- 当前专利权人地址: JP Tokyo US NY Armonk
- 代理机构: Law Offices of Mark L. Berrier
- 主分类号: H03K19/20
- IPC分类号: H03K19/20
摘要:
Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.
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