Invention Grant
US07219270B1 Device and method for using a lessened load to measure signal skew at the output of an integrated circuit
有权
使用减轻负载来测量集成电路输出端的信号偏移的装置和方法
- Patent Title: Device and method for using a lessened load to measure signal skew at the output of an integrated circuit
- Patent Title (中): 使用减轻负载来测量集成电路输出端的信号偏移的装置和方法
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Application No.: US10719878Application Date: 2003-11-21
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Publication No.: US07219270B1Publication Date: 2007-05-15
- Inventor: Jeffrey S. Brown , Craig R. Chafin
- Applicant: Jeffrey S. Brown , Craig R. Chafin
- Applicant Address: US CA Milpitas
- Assignee: LSI Logic Corporation
- Current Assignee: LSI Logic Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Daffer McDaniel, LLP
- Main IPC: G11B20/20
- IPC: G11B20/20

Abstract:
A device and method are provided for testing the timing of an output signal from a circuit. The output signal can be sent from a circuit contained within a portion of an integrated circuit, and represents a response to a test pattern or stimuli applied to that circuit. The output signal is compared to an expected output signal to determine skew of that signal relative to the clocking of the circuit. Testing the output signal involves placing a characterization path within the functional path of the output signal, between the circuits being tested and an output terminal that can receive a measurement device. By placing the characterization path into the functional path, the output signal sees only a single load gate terminal of, for example, a logic gate. The reduced loading not only positively impacts the normal operation of the output signal, but also beneficially minimizes the possibility of any inaccuracies in the characterization testing.
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