发明授权
- 专利标题: Correlator and delay lock loop circuit
- 专利标题(中): 相关器和延迟锁环电路
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申请号: US10625337申请日: 2003-07-22
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公开(公告)号: US07224720B2公开(公告)日: 2007-05-29
- 发明人: Yasuyuki Oishi , Kazuo Nagatani , Hajime Hamada , Yoshihiko Asano
- 申请人: Yasuyuki Oishi , Kazuo Nagatani , Hajime Hamada , Yoshihiko Asano
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Katten Muchin Rosenman LLP
- 优先权: JP10-203237 19980717
- 主分类号: H04B1/69
- IPC分类号: H04B1/69 ; H03D3/24
摘要:
The present invention reduces the scale of circuitry and shortens the code phase detection time needed to achieve initial synchronization. In a correlator for calculating correlation between a received spreading code contained in a received spread-spectrum signal and a reference spreading code, a combined code generator is included. The combined code generator outputs a combined spreading code by weighting and combining a plurality of phase-shifted reference spreading codes A1–AM. Further, an arithmetic circuit calculates correlation between the received spreading code and the plurality of phase-shifted reference spreading codes simultaneously. A phase detection circuit detects the phase difference between the received spreading code and a reference spreading code, namely the phase of the received spreading code from the results of the arithmetic operation.
公开/授权文献
- US20040258138A1 Correlator and delay lock loop circuit 公开/授权日:2004-12-23
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