Invention Grant
US07227384B2 Scan friendly domino exit and domino entry sequential circuits
有权
扫描友好的多米诺骨牌出口和多米诺骨牌进入顺序回路
- Patent Title: Scan friendly domino exit and domino entry sequential circuits
- Patent Title (中): 扫描友好的多米诺骨牌出口和多米诺骨牌进入顺序回路
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Application No.: US11201559Application Date: 2005-08-11
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Publication No.: US07227384B2Publication Date: 2007-06-05
- Inventor: Mondira Pant , Paul Gronowski , Randy Allmon , Manjunath Bhat , David Lin
- Applicant: Mondira Pant , Paul Gronowski , Randy Allmon , Manjunath Bhat , David Lin
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Lee & Hayes, PLLC
- Main IPC: H03K19/20
- IPC: H03K19/20

Abstract:
A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.
Public/Granted literature
- US20070035331A1 Scan friendly domino exit and domino entry sequential circuits Public/Granted day:2007-02-15
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