Provided is an input/output line sharing apparatus of a semiconductor memory device. In this apparatus, a global input/output line is shared by a data line signal and a test mode signal, and an input/output line between test mode signals is shared. The apparatus comprises a global input/output line, a first control signal generating unit configured to generate a test mode control signal from a test mode register set signal, a multiplexer configured to output a signal selected from a data line signal and a test mode signal to the global input/output line in response to the test mode control signal, and a latch unit configured to store the test mode signal outputted from the global input/output line in response to the test mode control signal.