Invention Grant
US07233512B2 Content addressable memory circuit with improved memory cell stability
有权
内存可寻址存储器电路，具有改善的存储单元稳定性
- Patent Title: Content addressable memory circuit with improved memory cell stability
- Patent Title (中): 内存可寻址存储器电路，具有改善的存储单元稳定性
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Application No.: US11048224Application Date: 2005-02-01
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Publication No.: US07233512B2Publication Date: 2007-06-19
- Inventor: Mark Lysinger , Francois Jacquet , Phillippe Roche
- Applicant: Mark Lysinger , Francois Jacquet , Phillippe Roche
- Applicant Address: US TX Carrollton FR
- Assignee: STMicroelectronics, Inc.,STMicroelectronics SA
- Current Assignee: STMicroelectronics, Inc.,STMicroelectronics SA
- Current Assignee Address: US TX Carrollton FR
- Agent Lisa K. Jorgenson; Christopher F. Regan
- Main IPC: G11C15/00
- IPC: G11C15/00
Abstract:
A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.
Public/Granted literature
- US20060171183A1 Content addressable memory circuit with improved memory cell stability Public/Granted day:2006-08-03
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