Invention Grant
US07234017B2 Computer system architecture for a processor connected to a high speed bus transceiver
有权
用于连接到高速总线收发器的处理器的计算机系统架构
- Patent Title: Computer system architecture for a processor connected to a high speed bus transceiver
- Patent Title (中): 用于连接到高速总线收发器的处理器的计算机系统架构
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Application No.: US11064745Application Date: 2005-02-24
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Publication No.: US07234017B2Publication Date: 2007-06-19
- Inventor: Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
- Applicant: Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Martin & Associates, LLC
- Agent Derek P. Martin
- Main IPC: G06F13/36
- IPC: G06F13/36
Abstract:
A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
Public/Granted literature
- US20060190668A1 Computer system architecture Public/Granted day:2006-08-24
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