发明授权
- 专利标题： Semiconductor device having isolation region and method of manufacturing the same
- 专利标题（中）： 具有隔离区域的半导体器件及其制造方法
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申请号： US10793923申请日： 2004-03-08
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公开(公告)号： US07238563B2公开(公告)日： 2007-07-03
- 发明人: Norihisa Arai , Takeshi Nakano , Koki Ueno , Akira Shimizu
- 申请人： Norihisa Arai , Takeshi Nakano , Koki Ueno , Akira Shimizu
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权： JP2003-063735 20030310
- 主分类号： H01L21/336
- IPC分类号： H01L21/336
摘要：
A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.
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