Invention Grant
- Patent Title: Voltage tolerant protection circuit for input buffer
- Patent Title (中): 输入缓冲器的耐压保护电路
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Application No.: US11143094Application Date: 2005-06-02
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Publication No.: US07239176B2Publication Date: 2007-07-03
- Inventor: Nitin Gupta
- Applicant: Nitin Gupta
- Applicant Address: IN Uttar Pradesh
- Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee: STMicroelectronics Pvt. Ltd.
- Current Assignee Address: IN Uttar Pradesh
- Agency: Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
- Agent Lisa K. Jorgenson; Jon A. Gibbons
- Priority: IN1009/DEL/2004 20041021
- Main IPC: H03K19/094
- IPC: H03K19/094

Abstract:
An improved voltage tolerant protection circuit for input buffer comprising a transmission gate circuit receiving input from the pad for passing the input signal to the input of the input buffer, a control signal generator electrically coupled between the transmission gate circuit and the pad to provide a control signal for operating the transmission gate circuit, and an N-Well generation circuit electrically coupled between the pad and the transmission gate circuit, and also electrically coupled to the control signal generator for generating a bias signal for the transmission gate circuit and the control signal generator. Thus, the present invention provides a voltage tolerant protection circuit that prevents electrical stress on transistors, minimizes power supply consumption and transfers signals without any change in amplitude.
Public/Granted literature
- US20060087340A1 Voltage tolerant protection circuit for input buffer Public/Granted day:2006-04-27
Information query
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