Invention Grant
- Patent Title: Method of forming a dual damascene structure
- Patent Title (中): 形成双镶嵌结构的方法
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Application No.: US10789083Application Date: 2004-02-27
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Publication No.: US07241682B2Publication Date: 2007-07-10
- Inventor: Bang-Chein Ho , Jian-Hong Chen , Da-Jhong Ou Yang
- Applicant: Bang-Chein Ho , Jian-Hong Chen , Da-Jhong Ou Yang
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Seminconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Seminconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Thomas, Kayden, Horstemeyer & Risley
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
An improved method of forming an integrated circuit that includes a dual damascene interconnect is described. A contact via hole is formed in a dielectric layer disposed above a semiconductor substrate. A protective layer is disposed on top of the dielectric layer and in the contact via hole, and subsequently forming as a recessed plug in the via, followed by etching to form a trench to complete formation of a dual damascene opening.
Public/Granted literature
- US20050191840A1 Method of forming a dual damascene structure Public/Granted day:2005-09-01
Information query
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