Invention Grant
- Patent Title: Memory module with parallel testing
- Patent Title (中): 内存模块并行测试
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Application No.: US11086059Application Date: 2005-03-22
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Publication No.: US07246280B2Publication Date: 2007-07-17
- Inventor: Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
- Applicant: Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agent Monica H. Choi
- Priority: KR10-2004-0019628 20040323; KR10-2004-0070025 20040902
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.
Public/Granted literature
- US20050216809A1 Memory module with parallel testing Public/Granted day:2005-09-29
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