发明授权
- 专利标题: Integrated circuit system using dual damascene process
- 专利标题(中): 集成电路系统采用双镶嵌工艺
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申请号: US11160624申请日: 2005-06-30
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公开(公告)号: US07253097B2公开(公告)日: 2007-08-07
- 发明人: Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
- 申请人: Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
- 申请人地址: SG Singapore
- 专利权人: Chartered Semiconductor Manufacturing, Ltd.
- 当前专利权人: Chartered Semiconductor Manufacturing, Ltd.
- 当前专利权人地址: SG Singapore
- 代理商 Mikio Ishimaru
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.
公开/授权文献
- US20070001303A1 INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS 公开/授权日:2007-01-04
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