Invention Grant
US07254149B2 Submount, pedestal, and bond wire assembly for a transistor outline package with reduced bond wire inductance 有权
用于晶体管外形封装的底座,基座和接合线组件,具有降低的接合线电感

Submount, pedestal, and bond wire assembly for a transistor outline package with reduced bond wire inductance
Abstract:
The present invention relates generally to optoelectronic devices, and particularly to a submount, pedestal, and bond wire assembly for a transistor outline package. A bottom surface of the submount is connected to a top surface of the pedestal. Each bond wire in a bond wire set is connected to a position on the top surface of the submount, and to a position on the signal line. The signal line is positioned a first distance from the position on the top surface of the submount and a second distance from the pedestal. The submount is sized such that a portion of the bottom and the top surface of the submount extends beyond the top surface of the pedestal such that the first distance is less than the second distance.
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