发明授权
US07263142B2 Apparatus and method for synchronizing symbol timing using timing loop controller
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使用定时环路控制器同步符号定时的装置和方法
- 专利标题: Apparatus and method for synchronizing symbol timing using timing loop controller
- 专利标题(中): 使用定时环路控制器同步符号定时的装置和方法
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申请号: US10722103申请日: 2003-11-24
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公开(公告)号: US07263142B2公开(公告)日: 2007-08-28
- 发明人: PanSoo Kim , Young Wan Kim , Nae-soo Kim
- 申请人: PanSoo Kim , Young Wan Kim , Nae-soo Kim
- 申请人地址: KR
- 专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人地址: KR
- 代理机构: Blakely Sokoloff Taylor & Zafman
- 优先权: KR10-2002-0074005 20021126
- 主分类号: H04L27/06
- IPC分类号: H04L27/06
摘要:
A timing loop controller for multilevel modulation scheme is disclosed. The timing loop controller includes a first to fourth computing unit for computing a timing error between an input timing of digital signals and a sampling timing; a first to fourth quantization unit for controlling a direction and an error value of the timing error; a first and second sign detection unit for detecting sign change according to results; a zero crossing detection unit for detecting zero crossing at I axis and Q axis; and a timing error control unit for controlling the timing error value in case there is no sign change. The present invention can increase a zitter performance of timing error according to the signal-to-noise ratio by detecting the timing error, outputting the timing error and controlling the timing error output value only in case there is sign change by additionally equipping the sign variation detector.
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