Invention Grant
US07265045B2 Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging 有权
用于制造用于芯片级封装的热适应性半导体芯片布线结构的方法

  • Patent Title: Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
  • Patent Title (中): 用于制造用于芯片级封装的热适应性半导体芯片布线结构的方法
  • Application No.: US10925302
    Application Date: 2004-08-24
  • Publication No.: US07265045B2
    Publication Date: 2007-09-04
  • Inventor: Jin-Yuan LeeEric Lin
  • Applicant: Jin-Yuan LeeEric Lin
  • Applicant Address: TW Hsin-Chu
  • Assignee: Megica Corporation
  • Current Assignee: Megica Corporation
  • Current Assignee Address: TW Hsin-Chu
  • Agency: Saile Ackerman LLC
  • Agent Stephen B. Ackerman; Rosemary L. S. Pike
  • Main IPC: H01L21/44
  • IPC: H01L21/44
Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging
Abstract:
A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.
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