Invention Grant
- Patent Title: Electrically rewritable nonvolatile semiconductor memory device
- Patent Title (中): 电可重写非易失性半导体存储器件
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Application No.: US11246215Application Date: 2005-10-11
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Publication No.: US07266016B2Publication Date: 2007-09-04
- Inventor: Yasushi Kameda
- Applicant: Yasushi Kameda
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- Priority: JP2004-331968 20041116
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/04

Abstract:
A clamp circuit is connected to one-side ends of first and second bit lines which are adjacent in a memory cell array and a data cache is connected to the other ends thereof. The first and second bit lines are selectively divided into plural portions by use of first and second switching elements. The data cache, clamp circuit and first and second switching elements are controlled by use of a control circuit and the bit line to which a memory cell of an address to be written is connected is precharged by use of the clamp circuit or data cache and the other bit line is shielded by the clamp circuit.
Public/Granted literature
- US20060104117A1 Electrically rewritable nonvolatile semiconductor memory device Public/Granted day:2006-05-18
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