Invention Grant
- Patent Title: Resistor ladder interpolation for PGA and DAC
- Patent Title (中): PGA和DAC的电阻梯形图插补
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Application No.: US10926407Application Date: 2004-08-26
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Publication No.: US07271755B2Publication Date: 2007-09-18
- Inventor: Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
- Applicant: Jan Mulder , Franciscus Maria Leonardus van der Goes , Jan Westra , Rudy van der Plassche
- Applicant Address: US CA Irvine
- Assignee: Broadcom Corporation
- Current Assignee: Broadcom Corporation
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox PLLC
- Main IPC: H03M1/12
- IPC: H03M1/12 ; H03M1/78 ; G06F17/17
Abstract:
A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
Public/Granted literature
- US20050068216A1 Resistor ladder interpolation for PGA and DAC Public/Granted day:2005-03-31
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