Invention Grant
- Patent Title: Digital phase locked loop
- Patent Title (中): 数字锁相环
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Application No.: US10137986Application Date: 2002-05-01
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Publication No.: US07272175B2Publication Date: 2007-09-18
- Inventor: Younggyun Kim , Jaekyun Moon
- Applicant: Younggyun Kim , Jaekyun Moon
- Applicant Address: US CA Santa Clara
- Assignee: DSP Group Inc.
- Current Assignee: DSP Group Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Shumaker & Sieffert, P.A.
- Main IPC: H04L27/14
- IPC: H04L27/14

Abstract:
Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.
Public/Granted literature
- US20030053564A1 Digital phase locked loop Public/Granted day:2003-03-20
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