发明授权
- 专利标题: Methods of forming integrated circuit devices having metal interconnect layers therein
-
申请号: US11216686申请日: 2005-08-31
-
公开(公告)号: US07282451B2公开(公告)日: 2007-10-16
- 发明人: Duk Ho Hong , Kyoung Woo Lee , Markus Naujok , Roman Knoefler
- 申请人: Duk Ho Hong , Kyoung Woo Lee , Markus Naujok , Roman Knoefler
- 申请人地址: KR DE
- 专利权人: Samsung Electronics Co., Ltd.,Infineon Technologies AG
- 当前专利权人: Samsung Electronics Co., Ltd.,Infineon Technologies AG
- 当前专利权人地址: KR DE
- 代理机构: Myers Bigel Sibley & Sajovec PA
- 主分类号: H01L21/302
- IPC分类号: H01L21/302
摘要:
Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.
公开/授权文献
信息查询
IPC分类: