发明授权
US07287171B1 Systems and methods for reducing static and total power consumption in programmable logic device architectures
有权
用于减少可编程逻辑器件架构中的静态和总功耗的系统和方法
- 专利标题： Systems and methods for reducing static and total power consumption in programmable logic device architectures
- 专利标题（中）： 用于减少可编程逻辑器件架构中的静态和总功耗的系统和方法
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申请号： US10796502申请日： 2004-03-08
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公开(公告)号： US07287171B1公开(公告)日： 2007-10-23
- 发明人: David Mendel , Vaughn Betz
- 申请人： David Mendel , Vaughn Betz
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Ropes & Gray LLP
- 代理商 Jeffrey H. Ingerman
- 主分类号： G06F1/00
- IPC分类号： G06F1/00 ; G06F11/30
摘要：
A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the synthesis, placement, routing, and period following routing of the programmable logic device.