发明授权
- 专利标题: Voltage controlled clock synthesizer
- 专利标题(中): 电压时钟合成器
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申请号: US11270957申请日: 2005-11-10
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公开(公告)号: US07288998B2公开(公告)日: 2007-10-30
- 发明人: Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
- 申请人: Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Derrick C. Wei
- 申请人地址: US TX Austin
- 专利权人: Silicon Laboratories Inc.
- 当前专利权人: Silicon Laboratories Inc.
- 当前专利权人地址: US TX Austin
- 代理机构: Zagorin O'Brien Graham LLP
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.
公开/授权文献
- US20060119437A1 Voltage controlled clock synthesizer 公开/授权日:2006-06-08