发明授权
US07299440B2 Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium
失效
半导体集成电路包括标准单元，标准单元布局设计方法和布局设计软件产品存储在计算机可读记录介质中
- 专利标题： Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium
- 专利标题（中）： 半导体集成电路包括标准单元，标准单元布局设计方法和布局设计软件产品存储在计算机可读记录介质中
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申请号： US10980171申请日： 2004-11-04
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公开(公告)号： US07299440B2公开(公告)日： 2007-11-20
- 发明人: Takeshi Yoshida , Naoyuki Tamura , You Yamamoto
- 申请人： Takeshi Yoshida , Naoyuki Tamura , You Yamamoto
- 申请人地址： JP Tokyo
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权： JP2004-057276 20040302
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
According to the present invention, there is provided a semiconductor integrated circuit layout design method of laying out standard cells by using a layout apparatus including an input unit, an arithmetic unit, and a storage unit, comprising, causing the arithmetic unit to calculate an area necessary for layout of each standard cell by using data about a plurality of kinds of standard cells having different heights in a row direction, which is stored in the storage unit in advance, causing the arithmetic unit to calculate the numbers of stages of row regions having heights corresponding to the standard cells on the basis of the calculated area, and causing the arithmetic unit to lay out the standard cells in the corresponding row regions.
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