A phase locked loop (PLL) having an improved phase unlock detection function generates a clock pulse signal at a frequency from a synchronization signal of a cathode ray tube (CRT) monitor and includes a phase frequency detector (PFD), a charge pump, a loop filter, a Voltage Controlled Oscillator (VCO), a divider, a phase unlock detection circuit, a phase lock/unlock detection circuit, and an output circuit. The phase unlock detection circuit detects an initial generation of a phase unlock from the up or down signal, outputs a first detection signal, and outputs an internal control signal according to the up or down signal. The phase lock/unlock detection circuit outputs a second detection signal, in response to the internal control signal and the first detection signal. The output circuit performs a logic operation on the first detection signal and the second detection signal and outputs a third detection signal.