发明授权
- 专利标题: SOI device with reduced junction capacitance
- 专利标题(中): 具有降低的结电容的SOI器件
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申请号: US10997597申请日: 2004-11-24
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公开(公告)号: US07323370B2公开(公告)日: 2008-01-29
- 发明人: Toshiharu Furukawa
- 申请人: Toshiharu Furukawa
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Schmeiser, Olsen & Watts
- 代理商 Anthony J. Canale
- 主分类号: H01L21/84
- IPC分类号: H01L21/84
摘要:
An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.
公开/授权文献
- US20050087804A1 SOI device with reduced junction capacitance 公开/授权日:2005-04-28