A multiplexer includes an encoder. The encoder includes: flip-flop circuits that output two signals having a transmission rate of B/2 at a frequency of B/2, while holding signals of each signal; an adder that adds the respective signals output from the flip-flop circuits and outputs the added signal; and a delay unit that delays the signal output from the flip-flop circuit by the time of 1/B, with respect to the signal output from the flip-flop circuit, and outputs the signal delayed to the adder.