- 专利标题： Semiconductor memory device and defect remedying method thereof
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申请号： US11714867申请日： 2007-03-07
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公开(公告)号： US07345929B2公开(公告)日： 2008-03-18
- 发明人: Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
- 申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
- 申请人地址： JP Tokyo JP Tokyo
- 专利权人： Hitachi, Ltd.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人： Hitachi, Ltd.,Hitachi ULSI Systems Co., Ltd.
- 当前专利权人地址： JP Tokyo JP Tokyo
- 代理机构： Antonelli, Terry, Stout & Kraus, LLP.
- 优先权： JP63-277132 19881101; JP63-279239 19881107; JP1-14423 19890124; JP1-65840 19890320
- 主分类号： G11C7/10
- IPC分类号： G11C7/10
摘要：
A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.