发明授权
US07350124B2 Method and apparatus for accelerating through-the pins LBIST simulation
失效
用于加速通过引脚LBIST模拟的方法和装置
- 专利标题: Method and apparatus for accelerating through-the pins LBIST simulation
- 专利标题(中): 用于加速通过引脚LBIST模拟的方法和装置
-
申请号: US11252512申请日: 2005-10-18
-
公开(公告)号: US07350124B2公开(公告)日: 2008-03-25
- 发明人: Tilman Gloekler , Christian Habermann , Naoki Kiryu , Joachim Kneisel , Johannes Koesters
- 申请人: Tilman Gloekler , Christian Habermann , Naoki Kiryu , Joachim Kneisel , Johannes Koesters
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Francis Lammes; Stephen J. Walder, Jr.; D'Ann N. Rifai
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.
公开/授权文献
信息查询