A switching circuit (112) is controlled by an in-slot interface-noise-power-control output circuit (115) to output an in-slot interface noise power (107-n) to a past-slot interference-noise-power memory (110), if there is no estimated value for an interference noise power of finger n of one slot before. If the interference noise power of the one slot before is not estimated and yet there exists an interference noise power which has been once estimated, the past-slot interference-noise-power memory (110) stores therein an interference noise power in a last slot which has been valid. An inter-slot averaging processing is performed between the interference noise power (111-n) from the past-slot interference-noise-power memory (110) and an estimated value (107-n) for the interference noise power in the current slot.