发明授权
- 专利标题: Assertion handling for timing model extraction
- 专利标题(中): 定时模型提取的断言处理
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申请号: US10313247申请日: 2002-12-06
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公开(公告)号: US07356451B2公开(公告)日: 2008-04-08
- 发明人: Cho Woo Moon , Harish Kriplani , Krishna Prasad Belkhale
- 申请人: Cho Woo Moon , Harish Kriplani , Krishna Prasad Belkhale
- 申请人地址: US CA San Jose
- 专利权人: Cadence Design Systems, Inc.
- 当前专利权人: Cadence Design Systems, Inc.
- 当前专利权人地址: US CA San Jose
- 代理机构: Bingham McCutchen LLP
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/45
摘要:
Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.
公开/授权文献
- US20030120474A1 Assertion handling for timing model extraction 公开/授权日:2003-06-26
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