Invention Grant
- Patent Title: Integrated circuit and method
- Patent Title (中): 集成电路及方法
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Application No.: US11145663Application Date: 2005-06-06
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Publication No.: US07361599B2Publication Date: 2008-04-22
- Inventor: Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
- Applicant: Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H01L21/302
- IPC: H01L21/302
Abstract:
A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
Public/Granted literature
- US20050227378A1 Integrated circuit and method Public/Granted day:2005-10-13
Information query
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