发明授权
- 专利标题： Method and apparatus of stress relief in semiconductor structures
- 专利标题（中）： 半导体结构中应力消除的方法和装置
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申请号： US10439874申请日： 2003-05-16
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公开(公告)号： US07368804B2公开(公告)日： 2008-05-06
- 发明人: Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
- 申请人： Mark Hoinkis , Matthias Hierlemann , Gerald Friese , Andy Cowley , Dennis J. Warner , Erdem Kaltalioglu
- 申请人地址： DE Munich
- 专利权人： Infineon Technologies AG
- 当前专利权人： Infineon Technologies AG
- 当前专利权人地址： DE Munich
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： H01L23/58
- IPC分类号： H01L23/58 ; H01L23/48
摘要：
A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
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