Invention Grant
- Patent Title: Stacked module systems and methods
- Patent Title (中): 堆叠模块系统和方法
-
Application No.: US10836855Application Date: 2004-04-30
-
Publication No.: US07371609B2Publication Date: 2008-05-13
- Inventor: Julian Partridge , James Douglas Wehrly, Jr.
- Applicant: Julian Partridge , James Douglas Wehrly, Jr.
- Applicant Address: US TX Austin
- Assignee: Staktek Group L.P.
- Current Assignee: Staktek Group L.P.
- Current Assignee Address: US TX Austin
- Agency: Fish & Richardson P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a preferred embodiment in accordance with the invention, a form standard associated with one or more CSPs provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the contacts of the lower CSP will be compressed before flex circuitry is attached to a combination of the CSP and a form standard to create lower profile contacts between CSP and the flex circuitry.
Public/Granted literature
- US20040201091A1 Stacked module systems and methods Public/Granted day:2004-10-14
Information query
IPC分类: