Invention Grant
US07371640B2 Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same
失效
具有浮动阱型非易失性存储单元的半导体器件及其制造方法
- Patent Title: Semiconductor device with floating trap type nonvolatile memory cell and method for manufacturing the same
- Patent Title (中): 具有浮动阱型非易失性存储单元的半导体器件及其制造方法
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Application No.: US11378505Application Date: 2006-03-17
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Publication No.: US07371640B2Publication Date: 2008-05-13
- Inventor: Sang-Su Kim , Kwang-Wook Koh , Geum-Jong Bae , Ki-Chul Kim , Sung-Ho Kim , Jin-Hee Kim , In-Wook Cho
- Applicant: Sang-Su Kim , Kwang-Wook Koh , Geum-Jong Bae , Ki-Chul Kim , Sung-Ho Kim , Jin-Hee Kim , In-Wook Cho
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Mills & Onello LLP
- Priority: KR03-52896 20030730
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially. The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.
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