Invention Grant
US07375398B2 High voltage FET gate structure 有权
高压FET栅极结构

High voltage FET gate structure
Abstract:
A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.
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