Invention Grant
- Patent Title: Stress liner for integrated circuits
- Patent Title (中): 集成电路应力衬垫
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Application No.: US11350160Application Date: 2006-02-07
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Publication No.: US07384833B2Publication Date: 2008-06-10
- Inventor: Igor Polishchuk , Krishnaswamy Ramkumar , Sagy Charel Levy
- Applicant: Igor Polishchuk , Krishnaswamy Ramkumar , Sagy Charel Levy
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Okamoto & Benedicto LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234

Abstract:
In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.
Public/Granted literature
- US20070184597A1 Stress liner for integrated circuits Public/Granted day:2007-08-09
Information query
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