Invention Grant
US07393765B2 Low temperature CVD process with selected stress of the CVD layer on CMOS devices
有权
低温CVD工艺，CMOS器件上CVD层的选择应力
- Patent Title: Low temperature CVD process with selected stress of the CVD layer on CMOS devices
- Patent Title (中): 低温CVD工艺，CMOS器件上CVD层的选择应力
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Application No.: US11788523Application Date: 2007-04-19
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Publication No.: US07393765B2Publication Date: 2008-07-01
- Inventor: Hiroji Hanawa , Kartik Ramaswamy , Kenneth S. Collins , Amir Al-Bayati , Biagio Gallo , Andrew Nguyen
- Applicant: Hiroji Hanawa , Kartik Ramaswamy , Kenneth S. Collins , Amir Al-Bayati , Biagio Gallo , Andrew Nguyen
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Law Office of Robert M. Wallace
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/425
Abstract:
Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with a toroidal RF plasma current while applying an RF plasma bias voltage. The temperature of the workpiece is held below a threshold photoresist removal temperature. The RF bias voltage is held at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.
Public/Granted literature
- US20070212811A1 Low temperature CVD process with selected stress of the CVD layer on CMOS devices Public/Granted day:2007-09-13
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