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发明授权
US07395454B1 Integrated circuit with integrated debugging mechanism for standard interface 有权
集成电路，集成调试机制，用于标准接口

Integrated circuit with integrated debugging mechanism for standard interface
摘要：
A circuit having a corresponding method comprises one or more circuits each to produce one or more status signals, wherein each of the status signals represents a status of a respective one of the one or more circuits; a memory; a memory controller to store a plurality of samples of the one or more status signals in the memory; a plurality of input/output terminals; an interface in communication with one or more of the input/output terminals; and a debug circuit to transfer the one or more samples of the status signals from the memory to the interface.
摘要（中）：

具有相应方法的电路包括一个或多个电路以产生一个或多个状态信号，其中每个状态信号表示一个或多个电路中的相应一个的状态; 记忆 存储器控制器，用于将所述一个或多个状态信号的多个样本存储在所述存储器中; 多个输入/输出端子; 与所述输入/输出端子中的一个或多个通信的接口; 以及调试电路，用于将状态信号的一个或多个样本从存储器传送到接口。

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